DK-DEV-5SGXEA7N【PDF 213/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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7-22

Leveling Circuitry

Figure 7-9: Avoiding Glitch on a Non-Consecutive Read Burst Waveform

This figure shows how to avoid postamble glitches using the HDR block.

Postamble

Postamble glitch

Preamble

SV51008

2014.01.10

DQS

Postamble Enable

dqsenable

Delayed by

1/2T logic

Leveling Circuitry

DDR3 SDRAM unbuffered modules use a fly-by clock distribution topology for better signal integrity. This

means that the CK/CK# signals arrive at each DDR3 SDRAM device in the module at different times. The

difference in arrival time between the first DDR3 SDRAM device and the last device on the module can be

as long as 1.6 ns.

The following figure shows the clock topology in DDR3 SDRAM unbuffered modules.

Figure 7-10: DDR3 SDRAM Unbuffered Module Clock Topology

DQS/DQ

DQS/DQ

DQS/DQ

DQS/DQ CK/CK#

DQS/DQ

DQS/DQ

DQS/DQ

DQS/DQ

FPGA

Because the data and read strobe signals are still point-to-point, take special care to ensure that the timing

relationship between the CK/CK# and DQS signals (t DQSS , t DSS , and t DSH ) during a write is met at every

device on the modules. In a similar way, read data coming back into the FPGA from the memory is also

staggered.

The Stratix V devices have leveling circuitry to address these two situations. There is one leveling circuit per

I/O sub-bank (for example, I/O sub-bank 1A, 1B, and 1C each has one leveling circuitry). These delay chains

are PVT-compensated by the same DQS delay settings as the DLL and DQS delay chains.

The DLL uses eight delay chain taps, such that each delay chain tap generates a 45° delay. The generated

clock phases are distributed to every DQS logic block that is available in the I/O sub-bank. The delay chain

Altera Corporation

External Memory Interfaces in Stratix V Devices

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